transcript on
if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -vlog01compat -work work +incdir+D:/fpga_class/DDS/DDS/src {D:/fpga_class/DDS/DDS/src/DDS_AD9767.v}
vlog -vlog01compat -work work +incdir+D:/fpga_class/DDS/DDS/src {D:/fpga_class/DDS/DDS/src/DDS_model.v}
vlog -vlog01compat -work work +incdir+D:/fpga_class/DDS/DDS/IP {D:/fpga_class/DDS/DDS/IP/sin_rom.v}
vlog -vlog01compat -work work +incdir+D:/fpga_class/DDS/DDS/IP {D:/fpga_class/DDS/DDS/IP/squ_rom.v}
vlog -vlog01compat -work work +incdir+D:/fpga_class/DDS/DDS/IP {D:/fpga_class/DDS/DDS/IP/tri_rom.v}
vlog -vlog01compat -work work +incdir+D:/fpga_class/DDS/DDS/IP {D:/fpga_class/DDS/DDS/IP/PLL_125.v}
vlog -vlog01compat -work work +incdir+D:/fpga_class/DDS/DDS/IP {D:/fpga_class/DDS/DDS/IP/ISSP.v}
vlog -vlog01compat -work work +incdir+D:/fpga_class/DDS/DDS/db {D:/fpga_class/DDS/DDS/db/pll_125_altpll.v}

vlog -vlog01compat -work work +incdir+D:/fpga_class/DDS/DDS/src {D:/fpga_class/DDS/DDS/src/DDS_AD9767_tb.v}

vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  DDS_AD9767_tb

add wave *
view structure
view signals
run -all
